SM320C6711-EP Datasheet, PDF (97/128 Pages) Texas Instruments – FLOATING-POINT DIGTAL SIGNAL PROCESSORS

SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
HOST-PORT INTERFACE TIMING
SGUS054 − AUGUST 2004
timing requirements for host-port interface cycles^†‡ (see Figure 46 through Figure 49) [C6711]
NO.
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low
3 tw(HSTBL)
Pulse duration, HSTROBE low
4 tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until
14 th(HRDYL-HSTBL) _{HRDY is active (low); otherwise, HPI writes will not complete properly.}
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low
C6711-100
C6711-150
MIN MAX
5
6§
4P
4P
5
3
5
6§
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
2
ns
2
ns
4§
ns
timing requirements for host-port interface cycles^†‡ (see Figure 46, through Figure 49) [C6711B]
C6711B-100
NO.
MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low
5
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low
4
3 tw(HSTBL)
Pulse duration, HSTROBE low
4P
4 tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
4P
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low
5
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low
3
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
5
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high
3
Hold time, HSTROBE low after HRDY low. HSTROBE should
14 th(HRDYL-HSTBL) not be inactivated until HRDY is active (low); otherwise, HPI
2
writes will not complete properly.
C6711B-150
C6711BGFNA-100
MIN
MAX
5
4
4P
4P
5
3
5
3
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
2
2
ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low
2
2
ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
§ _{Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing}
differences. IBIS analysis should be used to correctly model the system interface.
¶ _{Select signals include: HCNTL[1:0], HR/W, and HHWIL.}
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