TM4C1230C3PM Datasheet, PDF (963/1103 Pages) Texas Instruments – Tiva TM4C1230C3PM Microcontroller

Tiva^™ TM4C1230C3PM Microcontroller
Register 21: I²C Slave ACK Control (I2CSACKCTL), offset 0x820
This register enables the I²C slave to NACK for invalid data or command or ACK for valid data or
command. The I²C clock is pulled low after the last data bit until this register is written.
I2C Slave ACK Control (I2CSACKCTL)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
Offset 0x820
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ACKOVAL ACKOEN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
ACKOVAL
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
I²C Slave ACK Override Value
Value Description
0 An ACK is sent indicating valid data or command.
1 A NACK is sent indicating invalid data or command.
0
ACKOEN
RW
0
I²C Slave ACK Override Enable
Value Description
0 A response in not provided.
1 An ACK or NACK is sent according to the value written to the
ACKOVAL bit.
15.8
Register Descriptions (I²C Status and Control)
The remainder of this section lists and describes the I²C status and control registers, in numerical
order by address offset.
June 12, 2014
963
Texas Instruments-Production Data