TMS320F241_13 Datasheet, PDF (96/122 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
SPICLK
(Clock Polarity = 0)
SPICLK
(Clock Polarity = 1)
12
13
14
17
18
SPISOMI
SPISOMI Data Is Valid
SPISIMO
21
22
SPISIMO Data
Must Be Valid
Data Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until}
the SPI communication stream is complete.
Figure 36. SPI Slave Mode External Timing (Clock Phase = 1)
96
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