TM4C123GH6PM Datasheet, PDF (959/1409 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6PM Microcontroller
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx
SSInTx
MSB
MSB
4 to 16 bits
LSB Q
LSB
Note: Q is undefined.
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSInClk
SSInFss
SSInRx _LSB
SSInTx LSB
MSB
MSB
4 to16 bits
LSB
LSB
MSB
MSB
In this configuration, during idle periods:
■ SSInClk is forced Low
■ SSInFss is forced High
■ The transmit data line SSInTx is tristated
■ When the SSI is configured as a master, it enables the SSInClk pad
■ When the SSI is configured as a slave, it disables the SSInClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSInFss master signal being driven Low, causing slave data to be enabled onto the SSInRx
input line of the master. The master SSInTx output pad is enabled.
One half SSInClk period later, valid master data is transferred to the SSInTx pin. Once both the
master and slave data have been set, the SSInClk master clock pin goes High after one additional
half SSInClk period.
The data is now captured on the rising and propagated on the falling edges of the SSInClk signal.
June 12, 2014
959
Texas Instruments-Production Data