TM4C123GH6PM Datasheet, PDF (1182/1409 Pages) Texas Instruments – Tiva Microcontroller

Universal Serial Bus (USB) Controller
Bit/Field
7
6
5
4
3
Name
AUTOCL
AUTORQ
DMAEN
PIDERR
DMAMOD
Type
RW
RW
RW
RO
RW
Reset
0
Description
Auto Clear
Value Description
0 No effect.
1 Enables the RXRDY bit to be automatically cleared when a packet
of USBRXMAXPn bytes has been unloaded from the receive
FIFO. When packets of less than the maximum packet size are
unloaded, RXRDY must be cleared manually. Care must be taken
when using µDMA to unload the receive FIFO as data is read
from the receive FIFO in 4 byte chunks regardless of the value
of the MAXLOAD field in the USBRXMAXPn register, see “DMA
Operation” on page 1112.
0
Auto Request
Value Description
0 No effect.
1 Enables the REQPKT bit to be automatically set when the RXRDY
bit is cleared.
Note: This bit is automatically cleared when a short packet is
received.
0
DMA Request Enable
Value Description
0 Disables the µDMA request for the receive endpoint.
1 Enables the µDMA request for the receive endpoint.
Note:
3 TX and 3 RX endpoints can be connected to the µDMA
module. If this bit is set for a particular endpoint, the DMAARX,
DMABRX, or DMACRX field in the USB DMA Select
(USBDMASEL) register must be programmed
correspondingly.
0
PID Error
Value Description
0 No error.
1 Indicates a PID error in the received packet of an isochronous
transaction.
This bit is ignored in bulk or interrupt transactions.
0
DMA Request Mode
Value Description
0 An interrupt is generated after every µDMA packet transfer.
1 An interrupt is generated only after the entire µDMA transfer is
complete.
Note: This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
1182
Texas Instruments-Production Data
June 12, 2014