TMS320LF2407A_14 Datasheet, PDF (95/134 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
SPI slave mode timing parameters
Slave mode timing information is listed in the following tables.
SPI slave mode external timing parameters (clock phase = 0)^†‡ (see Figure 44)
NO.
12
13^§
14^§
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
t_w(SPCL)S
t_w(SPCH)S
15^{§ td(SPCH-SOMI)S}
t_{d(SPCL-SOMI)S}
t_{v(SPCL-SOMI)S}
16^§
t_{v(SPCH-SOMI)S}
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
MIN
4t_c(CO)‡
0.5t_c(SPC)S −10
0.5t_c(SPC)S −10
0.5t_c(SPC)S −10
0.5t_c(SPC)S −10
0.375t_c(SPC)S −10
0.375t_c(SPC)S −10
0.75t_c(SPC)S
0.75t_c(SPC)S
19^§
t_{su(SIMO-SPCL)S}
t_{su(SIMO-SPCH)S}
t_{v(SPCL-SIMO)S}
20^§
t_{v(SPCH-SIMO)S}
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0
0
0.5t_c(SPC)S
0.5t_c(SPC)S
† _{The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.}
‡ _{tc = system clock cycle time = 1/CLKOUT = tc(CO)}
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
MAX
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
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