TMS320LF2407A_14 Datasheet, PDF (56/134 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007
serial peripheral interface (SPI) module (continued)
Figure 15 is a block diagram of the SPI in slave mode.
SPIRXBUF.15 −0
SPIRXBUF
Buffer Register
Receiver
Overrun Flag
SPISTS.7
SPITXBUF.15 −0
16
SPITXBUF
Buffer Register
SPI INT FLAG
SPISTS.6
16
Overrun
INT ENA
SPICTL.4
SPI INT
ENA
SPICTL.0
To CPU
SPI Priority
SPIPRI.6
0 _{Level 1}
INT
1 _{Level 5}
INT
External
Connections
SPIDAT
Data Register
SPIDAT.15 −0
M
M
S
S
SW1
M
M
SPISIMO
Talk
SPICTL.1
S
S
SW2
SPISOMI
SPISTE^†
State Control
SPI Char ^{SPICCR.3 −0}
S
32 1 0
SPI Bit Rate
M
Internal
Clock
SPIBRR.6 −0
6543210
Master/Slave
SPICTL.2
SW3
Clock
S
Polarity
SPICCR.6
M
Clock
Phase
SPICTL.3
SPICLK
NOTE A: The diagram is shown in the slave mode.
† _{The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. See the following errata for restrictions}
on using the SPISTE pin:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata
(literature number SPRZ002)
TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers Silicon Errata (literature number SPRZ185)
Figure 15. Four-Pin Serial Peripheral Interface Module Block Diagram
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