TLV320AIC3110_16 Datasheet, PDF (95/132 Pages) Texas Instruments – TLV320AIC3110 Low-Power Audio Codec With Audio Processing and Stereo Class-D Speaker Amplifier

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TLV320AIC3110
SLAS647C – DECEMBER 2009 – REVISED MAY 2016
BIT
D
D6–D3
READ/
WRITE
R
R/W
D2-D0
R
RESET
VALUE
0
0111
000
Table 7-101. Page 0 / Register 69 (0x45): DRC Control 2
DESCRIPTION
Reserved. Write only the reset value to these bits.
DRC Hold Time
0000: DRC Hold Disabled
0001: DRC Hold Time = 32 DAC Word Clocks
0010: DRC Hold Time = 64 DAC Word Clocks
0011: DRC Hold Time = 128 DAC Word Clocks
0100: DRC Hold Time = 256 DAC Word Clocks
0101: DRC Hold Time = 512 DAC Word Clocks
0110: DRC Hold Time = 1024 DAC Word Clocks
0111: DRC Hold Time = 2048 DAC Word Clocks
1000: DRC Hold Time = 4096 DAC Word Clocks
1001: DRC Hold Time = 8192 DAC Word Clocks
1010: DRC Hold Time = 16 384 DAC Word Clocks
1011: DRC Hold Time = 32 768 DAC Word Clocks
1100: DRC Hold Time = 65 536 DAC Word Clocks
1101: DRC Hold Time = 98 304 DAC Word Clocks
1110: DRC Hold Time = 131 072 DAC Word Clocks
1111: DRC Hold Time = 163 840 DAC Word Clocks
Reserved. Write only the reset value to these bits.
BIT
D7–D4
READ/
WRITE
R/W
D3–D0 R/W
RESET
VALUE
0000
0000
Table 7-102. Page 0 / Register 70 (0x46): DRC Control 3
DESCRIPTION
0000: DRC attack rate = 4 dB per DAC Word Clock
0001: DRC attack rate = 2 dB per DAC word clock
0010: DRC attack rate = 1 dB per DAC word clock
...
1110: DRC attack rate = 2.4414e–5 dB per DAC word clock
1111: DRC attack rate = 1.2207e–5 dB per DAC word clock
Decay Rate is defined as DR / 2^{[bits D3-D0 value]} dB per DAC Word Clock, where DR = 0.015625 dB
0000: DRC decay rate (DR) = 0.015625 dB per DAC Word Clock
0001: DRC decay rate = DR / 2 dB per DAC Word Clock
0010: DRC decay rate = DR / 2² dB per DAC Word Clock
0011: DRC decay rate = DR / 2³ dB per DAC Word Clock
0100: DRC decay rate = DR / 2⁴ dB per DAC Word Clock
0101: DRC decay rate = DR / 2⁵ dB per DAC Word Clock
0110: DRC decay rate = DR / 2⁶ dB per DAC Word Clock
0111: DRC decay rate = DR / 2⁷ dB per DAC Word Clock
1000: DRC decay rate = DR / 2⁸ dB per DAC Word Clock
1001: DRC decay rate = DR / 2⁹ dB per DAC Word Clock
1010: DRC decay rate = DR / 2¹⁰ dB per DAC Word Clock
1011: DRC decay rate = DR / 2¹¹ dB per DAC Word Clock
1100: DRC decay rate = DR / 2¹² dB per DAC Word Clock
1101: DRC decay rate = DR / 2¹³ dB per DAC Word Clock
1110: DRC decay rate = DR / 2¹⁴ dB per DAC Word Clock
1111: DRC decay rate = DR / 2¹⁵ dB per DAC Word Clock
Table 7-103. Page 0 / Register 71 (0x47): Left Beep Generator ⁽¹⁾
BIT
READ/
WRITE
D7
R/W
D6
R/W
D5–D0 R/W
RESET
VALUE
0
0
00 0000
DESCRIPTION
0: Beep generator is disabled.
1: Beep generator is enabled (self-clearing based on beep duration).
Reserved. Write only reset value.
00 0000: Left-channel beep volume control = 2 dB
00 0001: Left-channel beep volume control = 1 dB
00 0010: Left-channel beep volume control = 0 dB
00 0011: Left-channel beep volume control = –1 dB
...
11 1110: Left-channel beep volume control = –60 dB
11 1111: Left-channel beep volume control = –61 dB
(1) The beep generator is only available in PRB_P25 DAC processing mode.
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