TLV320AIC3110_16 Datasheet, PDF (2/132 Pages) Texas Instruments – TLV320AIC3110 Low-Power Audio Codec With Audio Processing and Stereo Class-D Speaker Amplifier

TLV320AIC3110
SLAS647C – DECEMBER 2009 – REVISED MAY 2016
www.ti.com
1.4 Functional Block Diagram
SPLVDD SPRVDD SPLVSS
SPRVSS
HPVDD
HPVSS
AVDD
AVSS
MICBIAS
VOL/
MICDET
SPLP
SPLM
SPRP
SPRM
HPL
HPR
MIC1LP
MIC1RP
2 V/2.5 V/AVDD
7-Bit ADC P0/R116
P1/R33–R34
De-Pop
and
Soft-
Start
Left and Right Volume-
Control Register
P0/R116
Class-D Speaker
Driver
P1/R42
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
P1/R38
MIX_L
6 dB to 24 dB (6-dB Steps)
P1/R32
P1/R43
P1/R39
MIX_R
RC CLK
Audio Output Stage
Power Management
GPIO
I²C
P1/R30
Class A/B
Headphone/Lineout
Driver
P1/R40
P1/R31 0 dB to 9 dB (1-dB Steps)
P1/R44
P1/R41
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
P1/R36
MIX_L
P1/R37
MIX_R
MIX_R
MIX_L
MIC1LP
DAC_L
S
D-S
DAC
S
S
P1/R35
MIC1RP
DAC_R
S
D-S
DAC
Digital Vol
24 dB to
Mute
Processing
Blocks
P0/R63
S
P0/ PRB_P1–
S
R64–R65 PRB_P25
Selectable
Gain/Input
Impedance
Digital
Vol Ctl
P0/R71
P0/R72
0 to –63 dB
P1/R47
(1-dB Steps)
0 to 59.5 dB
(0.5-dB steps) Mono ADC
P0/R82–R83
S
P1/R48
D-S
ADC
P0/R86–R93
Digital Vol
–12..20 dB
Step = 0.5 dB
AGC
Digital Beep
Generator
Processing
Blocks
PRB_R4–
PRB_R18
Note: Normally,
MCLK is PLL input;
however, BCLK,
GPIO1, etc., can
also be PLL input.
PLL
Digital
Audio
Processing
and
Serial
Interface
MIC1LM
Input CM
P1/R50
S
VCOM
P1/R49
Selectable
Gain/Input
Impedance
OSC
RC CLK
GPIO1
SDA
SCL
MCLK
DOUT
WCLK
DIN
BCLK
RESET
DVDD
DVSS
IOVDD
IOVSS
Copyright © 2016, Texas Instruments Incorporated
2
Device Overview
Copyright © 2009–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLV320AIC3110