RM48L940 Datasheet, PDF (95/152 Pages) Texas Instruments – RM48Lx40 16/32-Bit RISC Flash Microcontroller

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RM48L940
RM48L740
RM48L540
SPNS175 – SEPTEMBER 2011
4.18 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the RM4x microcontroller. The
error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be
configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an
indicator to an external monitor circuit to put the system into a safe state.
4.18.1 Features
The features of the Error Signaling Module are:
• 128 interrupt/error channels are supported, divided into 3 different groups
– 64 channels with maskable interrupt and configurable error pin behavior
– 32 error channels with non-maskable interrupt and predefined error pin behavior
– 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability
4.18.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 4-35 shows the channel assignment for each group.
ERROR GROUP
Group1
Group2
Group3
Table 4-34. ESM Groups
INTERRUPT CHARACTERISTICS
maskable, low or high priority
non-maskable, high priority
no interrupt generated
INFLUENCE ON ERROR PIN
configurable
fixed
fixed
Table 4-35. ESM Channel Assignments
ERROR SOURCES
Reserved
MibADC2 - parity
DMA - MPU
DMA - parity
Reserved
DMA - imprecise read error
FMC - correctable error: bus1 and bus2 interfaces
(does not include accesses to EEPROM bank)
N2HET1/N2HET2 - parity
HET TU1/HET TU2 - parity
HET TU1/HET TU2 - MPU
PLL - Slip
Clock Monitor - interrupt
Reserved
DMA - imprecise write error
Reserved
VIM RAM - parity
Reserved
MibSPI1 - parity
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Copyright © 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
95
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