LM3S8C62 Datasheet, PDF (941/1097 Pages) Texas Instruments – Stellaris® LM3S8C62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8C62 Microcontroller
Register 54: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
Register 55: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
Register 56: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
This register specifies which digital comparator triggers from the ADC are used to generate a fault
condition. Each bit in the following register indicates whether the corresponding digital comparator
trigger is included in the fault condition. All enabled digital comparator triggers are ORed together
to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is
then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM
generator.
If the FLTSRC bit in the PWMnCTL register (see page 914) is clear, only the PWM Fault0 pin affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWM0 Fault Source 1 (PWM0FLTSRC1)
PWM0 base: 0x4002.8000
Offset 0x078
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DCMP7 DCMP6 DCMP5 DCMP4 DCMP3 DCMP2 DCMP1 DCMP0
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
Name
reserved
DCMP7
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Digital Comparator 7
Value Description
0 The trigger from digital comparator 7 is suppressed and cannot
generate a fault condition.
1 The trigger from digital comparator 7 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
July 24, 2012
941
Texas Instruments-Production Data