LM3S8C62 Datasheet, PDF (474/1097 Pages) Texas Instruments – Stellaris® LM3S8C62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
General-Purpose Timers
Figure 10-5. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
0xC350
GPTMTnR=GPTMnMR
0x411A
TnEN set
Output
Signal
TnPWML = 0
TnPWML = 1
Time
10.3.3
10.3.4
DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
The arbitration size of the μDMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 350 for more details about programming the μDMA controller.
Accessing Concatenated Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are
concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 498
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 499
■ GPTM Timer A (GPTMTAR) register [15:0], see page 506
■ GPTM Timer B (GPTMTBR) register [15:0], see page 507
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 508
474
July 24, 2012
Texas Instruments-Production Data