LM3S9U92 Datasheet, PDF (934/1407 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Ethernet Controller
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
18.5
Register Map
Table 18-4 on page 934 lists the Ethernet MAC and MII Management registers. The MAC register
addresses given are relative to the Ethernet base address of 0x4004.8000. The MII Management
registers are accessed using the MACMCTL register. Note that the Ethernet controller clocks must
be enabled before the registers can be programmed (see page 283). There must be a delay of 3
system clocks after the Ethernet module clock is enabled before any Ethernet module registers are
accessed. In addition, the Ethernet oscillator is powered down when the EPHY0 bit in the Run Mode
Clock Gating Control Register 2 (RCGC2) register is clear. After setting the EPHY0 bit, software
must wait 3.5 ms before accessing any of the MII Management registers.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 18-4 on page 934 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation.
Table 18-4. Ethernet Register Map
Offset Name
Type
Reset
Description
Ethernet MAC (Ethernet Offset)
0x000 MACRIS/MACIACK
0x004 MACIM
R/W1C
R/W
0x0000.0000
0x0000.007F
Ethernet MAC Raw Interrupt Status/Acknowledge
Ethernet MAC Interrupt Mask
See
page
937
940
934
January 22, 2012
Texas Instruments-Production Data