SM320LF2407A-EP Datasheet, PDF (93/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
E_DNL and E_INL for LF2407A
PARAMETER
EDNL‡
Differential nonlinearity error
EINL‡
Integral nonlinearity error
‡ _{Test conditions: VREFHI = VCCA , VREFLO = VSSA}
DESCRIPTION
Difference between the actual step width
and the ideal value
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
CLKOUT
30 MHz
30 MHz
MIN MAX UNIT
"3 LSB
"3 LSB
internal ADC module timings^† (see Figure 44)
MIN
MAX UNIT
tc(AD)
tw(SHC)
tw(SH)
tw(C)
td(SOC-SH)
td(EOC)
Cycle time, ADC prescaled clock
Pulse duration, total sample/hold and conversion time‡
Pulse duration, sample and hold time
Pulse duration, total conversion time
Delay time, start of conversion to beginning of sample and hold
Delay time, end of conversion to data loaded into result register
33.3
ns
500
ns
2tc(AD)§ 32tc(AD) ns
10tc(AD)
ns
2tc(CO)
ns
2tc(CO)
ns
td(ADCINT) Delay time, ADC flag to ADC interrupt
2tc(CO)
ns
† _{The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers}
Reference Guide: System and Peripherals (literature number SPRU357) for more details.
‡ _{The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC) .}
§ _{Can be varied by ACQ Prescaler bits in the ADCTRL1 register}
Bit Converted
ADC Clock
tc(AD)
9 8 76 5 4 3 2 10
ÁÁÁÁÁ ^{Analog Input}
EOC/Convert
Internal Start/
Sample Hold
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tw(C)
tw(SH)
Start of Convert
td(SOC−SH)
XFR to RESULTn
tw(SHC)
td(EOC)
td(ADCINT)
ADC Interrupt
Figure 44. Analog-to-Digital Internal Module Timing
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