SM320LF2407A-EP Datasheet, PDF (89/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external memory interface ready-on-read timings (continued)
timing requirements for an external memory interface ready-on-read with one software wait state
and one external wait state (see Figure 41)
th(RDY)COH
tsu(RDY)COH
td(COL-A)RD
Hold time, READY after CLKOUT high
Setup time, READY before CLKOUT high
Delay time, CLKOUT low to address valid
MIN
H − 2.5
H − 9.5
MAX
8
UNIT
ns
ns
ns
CLKOUT
PS, DS, IS
A[0:15]
W/R
R/W
D[0:15]
SW = 1 cycle
EXW = 1 cycle
Read Cycle
td(COL-A)RD
STRB
READY
tsu(RDY)COH
th(RDY)COH
RD
Figure 41. Ready-on-Read Timings With One Software Wait (SW) State and
One External Wait (EXW) State
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