LM4F110H5QR Datasheet, PDF (924/1155 Pages) Texas Instruments – Microcontroller

Synchronous Serial Interface (SSI)
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
SSIRx
0 MSB
LSB
4 to 16 bits
output data
8-bit control
LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 15-12 on page 924 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
t_Setup=(2*t_SSIClk)
t_Hold=t_SSIClk
SSIClk
SSIFss
15.3.5
SSIRx
First RX data to be
sampled by SSI slave
DMA Operation
The SSI peripheral provides an interface to the μDMA controller with separate channels for transmit
and receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL)
register. When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or
transmit channel when the associated FIFO can transfer data. For the receive channel, a single
transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is
asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit
channel, a single transfer request is asserted whenever at least one empty location is in the transmit
FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The
single and burst µDMA transfer requests are handled automatically by the μDMA controller depending
how the µDMA channel is configured. To enable µDMA operation for the receive channel, the
RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation
for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then
the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the
SSI interrupt vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the
SSI interrupt handler must be designed to handle the μDMA completion interrupt.
924
April 25, 2012
Texas Instruments-Advance Information