LM4F110H5QR Datasheet, PDF (28/1155 Pages) Texas Instruments – Microcontroller

Table of Contents
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 880
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 882
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 885
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 888
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 891
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 893
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 894
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 895
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 896
UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 897
UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 898
UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 899
UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 900
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 901
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 902
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 903
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 904
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 905
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 906
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 907
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 908
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 909
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 910
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 911
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 912
Synchronous Serial Interface (SSI) ............................................................................................ 913
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 928
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 930
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 932
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 933
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 935
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 936
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 937
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 939
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 941
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 942
Register 11: SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................... 943
Register 12: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 944
Register 13: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 945
Register 14: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 946
Register 15: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 947
Register 16: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 948
Register 17: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 949
Register 18: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 950
Register 19: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 951
Register 20: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 952
Register 21: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 953
Register 22: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 954
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April 25, 2012
Texas Instruments-Advance Information