TSB43AB23PDTG4 Datasheet, PDF (92/110 Pages) Texas Instruments – IEEE 1394a-2000 OHCI PHY/Link Layer Controller 

7 PHY Register Configuration
There are 16 accessible internal registers in the TSB43AB23 device. The configuration of the registers at addresses
0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The
selected page is set in base register 7h.
7.1 Base Registers
Table 7–1 shows the configuration of the base registers, and Table 7–2 shows the corresponding field descriptions.
The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as reserved in the following register configuration tables) is read as 0,
but is subject to future usage. All registers in address pages 2 through 6 are reserved.
ADDRESS
0000
0001
0010
0011
0100
0101
0110
0111
Table 7–1. Base Register Configuration
BIT POSITION
0
1
2
3
4
5
6
7
Physical ID
R
CPS
RHB
IBR
Gap_Count
Extended (111b)
Reserved
Total_Ports (0011b)
Max_Speed (010b)
Reserved
Delay (0000b)
LCtrl
C
Jitter (000b)
Pwr_Class
Watchdog
ISBR
Loop
Pwr_fail
Timeout Port_event Enab_accel Enab_multi
Reserved
Page_Select
Reserved
Port_Select
7–1