TMS570LS0432_17 Datasheet, PDF (92/110 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
www.ti.com
Table 7-16. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)^(1)(2)(3)(4)
NO.
1
2 ⁽⁶⁾
3 ⁽⁶⁾
4 ⁽⁶⁾
t_c(SPC)S
t_w(SPCH)S
t_w(SPCL)S
t_w(SPCL)S
t_w(SPCH)S
t_{d(SOMI-SPCL)S}
t_{d(SOMI-SPCH)S}
5 ⁽⁶⁾
6 ⁽⁶⁾
7 ⁽⁶⁾
t_{h(SPCL-SOMI)S}
t_{h(SPCH-SOMI)S}
t_{su(SIMO-SPCH)S}
t_{su(SIMO-SPCL)S}
t_{v(SPCH-SIMO)S}
t_{v(SPCL-SIMO)S}
t_{d(SPCH-SENAH)S}
8
t_{d(SPCL-SENAH)S}
9
t_{d(SCSL-SENAL)S}
10
t_{d(SCSL-SOMI)S}
PARAMETER
Cycle time, SPICLK⁽⁵⁾
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Dealy time, SPISOMI data valid after SPICLK low (clock
polarity = 0)
Delay time, SPISOMI data valid after SPICLK high (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
Hold time, SPISOMI data valid after SPICLK low (clock polarity
=1)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
High time, SPISIMO data valid after SPICLK high (clock
polarity = 0)
High time, SPISIMO data valid after SPICLK low (clock polarity
= 1)
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 0)
Delay time, SPIENAn high after last SPICLK low (clock polarity
= 1)
Delay time, SPIENAn low after SPICSn low (if new data has
been written to the SPI buffer)
Delay time, SOMI valid after SPICSn low (if new data has been
written to the SPI buffer)
MIN
40
14
14
14
14
2
2
4
4
2
2
1.5t_c(VCLK)
1.5t_c(VCLK)
t_f(ENAn)
t_c(VCLK)
MAX
t_rf(SOMI) + 20
t_rf(SOMI) + 20
2.5t_c(VCLK)+t_r(ENAn) + 22
2.5t_c(VCLK)+t_r(ENAn) + 22
t_c(VCLK)+t_f(ENAn)+ 27
2t_c(VCLK)+t_rf(SOMI)+ 28
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-6.
(4) t_c(VCLK) = interface clock cycle time = 1 /f_(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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Peripheral Information and Electrical Specifications
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