TMS570LS0432_17 Datasheet, PDF (20/110 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
www.ti.com
5.6 Wait States Required
The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states
required. There are no registers which need to be programmed for RAM wait states.
The TCM flash can support zero address and data wait states up to a CPU speed of 45 MHz in nonpipelined
mode.The flash supports a maximum CPU clock speed of 80 MHz in pipelined mode with no address wait states
and one data wait state.
The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN
0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT
0xFFF872B8[19:16]) as shown in Figure 5-1.
Flash Address Wait States
ASWSTEN
0
0MHz
Main Memory Data Wait States (Bank 0)
RWAIT
0
0MHz
45MHz
80MHz
1
80MHz
EEPROM Emulation Memory Wait States (Bank 7)
EWAIT
1
0MHz
2
50MHz
Figure 5-1. Wait States Scheme
67MHz
3
80MHz
The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main
memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.
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Specifications
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