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TMS320VC5506_13 Datasheet, PDF (92/117 Pages) Texas Instruments – Fixed-Point Digital Signal Processor | |||
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Electrical Specifications
5.9 External Interrupt Timings
Table 5â16 assumes testing over recommended operating conditions (see Figure 5â18).
Table 5â16. External Interrupt Timing Requirementsâ
NO.
I1 tw(INTH)A
Pulse width, interrupt high, CPU active
I2 tw(INTL)A
Pulse width, interrupt low, CPU active
â P = 1/CPU clock frequency in ns. For example, when running parts at 108 MHz, use P = 9.26 ns.
MIN MAX UNIT
2P
ns
3P
ns
I1
INTn
I2
Figure 5â18. External Interrupt Timings
5.10 Wake-Up From IDLE
Table 5â17 assumes testing over recommended operating conditions (see Figure 5â19).
Table 5â17. Wake-Up From IDLE Switching Characteristicsâ
NO.
PARAMETER
MIN TYP
ID1
td(WKPEVTL-CLKGEN)
Delay time, wake-up event low to clock generation enable
(CPU and clock domain idle)
1.25â¡
MAX UNIT
ms
ID2
th(CLKGEN-WKPEVTL)
Hold time, clock generation enable to wake-up event low
(CPU and clock domain in idle)
3P§
ns
ID3 tw(WKPEVTL)
Pulse width, wake-up event low
(for CPU idle only)
3P
ns
â P = 1/CPU clock frequency in ns. For example, when running parts at 108 MHz, use P = 9.26 ns.
⡠Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal characteristics
operating condition and the PC board layout and the parasitics.
§ Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx following
the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The number of interrupts
sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.
X1
RESET,
INTx
ID1
ID2
ID3
Figure 5â19. Wake-Up From IDLE Timings
92 SPRS375C
October 2006 â Revised January 2008
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