TMS320C5535_14 Datasheet, PDF (92/156 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Table 5-25. Timing Requirements for I2S
[I/O = 1.8 V]⁽¹⁾ (see Figure 5-24)
NO.
1 t_c(CLK)
Cycle time, I2S_CLK
MASTER
CV_DD = 1.05 V CV_DD = 1.3 V
MIN MAX MIN MAX
50 or
2P ⁽¹⁾
(2)
40 or
2P ⁽¹⁾
(2)
SLAVE
CV_DD = 1.05 V
MIN MAX
CV_DD = 1.3 V UNIT
MIN MAX
50 or
2P^{(1) (2)}
40 or
2P^{(1) (2)}
ns
2 t_w(CLKH)
Pulse duration, I2S_CLK high
25
3 t_w(CLKL)
Pulse duration, I2S_CLK low
25
t_su(RXV-CLKH)
Setup time, I2S_RX valid before
I2S CLK high (CLKPOL = 0)
5
7
t_su(RXV-CLKL)
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
5
t_h(CLKH-RXV)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
3
8
t_h(CLKL-RXV)
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
3
t_su(FSV-CLKH)
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
–
9
t_su(FSV-CLKL)
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
–
t_h(CLKH-FSV)
Hold time, I2S_FS valid after
I2S_CLK high (CLKPOL = 0)
–
10
t_h(CLKL-FSV)
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
–
20
25
20
ns
20
25
20
ns
5
5
5
ns
5
5
5
ns
3
3
3
ns
3
3
3
ns
–
15
15
ns
–
15
15
ns
–
t_w(CLKH) +
0.6 ⁽³⁾
t_w(CLKH) +
0.6 ⁽³⁾
ns
–
t_w(CLKL) +
0.6 ⁽³⁾
t_w(CLKL) +
0.6 ⁽³⁾
ns
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
Table 5-26. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 V, 2.75 V, or 2.5 V] (see Figure 5-24)
NO.
PARAMETER
1 t_c(CLK)
Cycle time, I2S_CLK
MASTER
CV_DD = 1.05
V
CV_DD = 1.3 V
MIN MAX MIN MAX
40 or
2P ⁽¹⁾
(2)
40 or
2P ⁽¹⁾
(2)
SLAVE
CV_DD = 1.05
V
CV_DD = 1.3 V
UNIT
MIN MAX MIN MAX
40 or
40 or
2P ⁽¹⁾
2P ⁽¹⁾
ns
(2)
(2)
2
t_w(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
20
20
20
t_w(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
20
20
20
3
t_w(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
20
20
20
t_w(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
20
20
20
t_dmax(CLKL- Output Delay time, I2S_CLK low to I2S_DX valid
4 ^DXV)
(CLKPOL = 0)
t_dmax(CLKH- Output Delay time, I2S_CLK high to I2S_DX
DXV)
valid (CLKPOL = 1)
0 15
0 15
0 14
0 14
0 15
0 15
t_dmax(CLKL- Delay time, I2S_CLK low to I2S_FS valid
5 ^FSV)
(CLKPOL = 0)
-1.1 14 -1.1 14
–
t_dmax(CLKH- Delay time, I2S_CLK high to I2S_FS valid
FSV)
(CLKPOL = 1)
-1.1 14 -1.1 14
–
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
20
ns
20
ns
20
ns
20
ns
0 15 ns
0 15 ns
– ns
– ns
92
Specifications
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