TMS320C5535_14 Datasheet, PDF (1/156 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

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TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
TMS320C5535, 'C5534, 'C5533, 'C5532 Fixed-Point Digital Signal Processors
1 Device Overview
1.1 Features
1
• CORE:
– High-Performance, Low-Power, TMS320C55x
Fixed-Point Digital Signal Processor
• 20-, 10-ns Instruction Cycle Time
• 50-, 100-MHz Clock Rate
• One or Two Instructions Executed per Cycle
• Dual Multiply-and-Accumulate Units (Up to
200 Million Multiply-Accumulates per Second
[MMACS])
• Two Arithmetic and Logic Units (ALUs)
• Three Internal Data and Operand Read
Buses and Two Internal Data and Operand
Write Buses
• Software-Compatible with C55x Devices
• Industrial Temperature Devices Available
– 320KB of Zero-Wait State On-Chip RAM,
Composed of:
• 64KB of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
• 256KB of Single-Access RAM (SARAM), 32
Blocks of 4K x 16-Bit
– 128KB of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
– Tightly Coupled FFT Hardware Accelerator
• PERIPHERAL:
– Direct Memory Access (DMA) Controller
• Four DMA with 4 Channels Each (16
Channels Total)
– Three 32-Bit General-Purpose (GP) Timers
• One Selectable as a Watchdog or GP
– Two Embedded Multimedia Card (eMMC) or
Secure Digital (SD) Interfaces
– Universal Asynchronous Receiver/Transmitter
(UART)
– Serial Port Interface (SPI) with Four Chip
Selects
– Master and Slave Inter-Integrated Circuit (I²C
Bus)
– Four Inter-IC Sound (I²S Bus) for Data
Transport
– Device USB Port with Integrated 2.0 High-
Speed PHY that Supports:
• USB 2.0 Full- and High-Speed Device
– LCD Bridge with Asynchronous Interface
– 10-Bit 4-Input Successive Approximation (SAR)
ADC
– IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
– 32 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
• Configure Up to 20 GPIO Pins at the Same
Time
• POWER:
– Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
– Three I/O Isolated Power Supply Domains: RTC
I/O, USB PHY, and DV_DDIO
– Three integrated LDOs (DSP_LDO, ANA_LDO,
and USB_LDO) to power the isolated domains:
DSP Core, Analog, and USB Core, respectively
– 1.05-V Core (50 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
– 1.3-V Core (100 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
• CLOCK:
– Real-Time Clock (RTC) with Crystal Input,
Separate Clock Domain, and Separate Power
Supply
– Low-Power Software Programmable Phase-
Locked Loop (PLL) Clock Generator
• BOOTLOADER:
– On-Chip ROM Bootloader (RBL) to Boot From
SPI EEPROM, SPI Serial Flash or I²C EEPROM
eMMC, SD, SDHC, UART, and USB
• PACKAGE:
– 144-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZHH Suffix)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.