DP83867IR Datasheet, PDF (92/130 Pages) Texas Instruments – High Immunity 10/100/1000 Ethernet Physical Layer Transceiver

DP83867IR, DP83867CR
SNLS484C – FEBRUARY 2015 – REVISED NOVEMBER 2015
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9.6.38 Receive Configuration Register (RXFCFG)
This register provides receive configuration for Wake on LAN (WoL).
BIT
15:12
11
10:9
8
7
6
5
4
3
2
1
0
Table 48. Receive Configuration Register (RXFCFG), Address 0x0134
BIT NAME
RESERVED
WOL_OUT_CLEAR
WOL_OUT_STRETCH
DEFAULT
0, RO
0, RW, SC
00, RW
WOL_OUT_MODE
0, RW
ENHANCED_MAC_SUPPORT 0, RW
RESERVED
SCRON_EN
WAKE_ON_UCAST
RESERVED
WAKE_ON_BCAST
WAKE_ON_PATTERN
WAKE_ON_MAGIC
0, RO
0, RW
0, RW
0, RO
1, RW
0, RW
0, RW
DESCRIPTION
RESERVED
Clear Wake on LAN Output:
This bit is only applicable when configured for level mode.
1 = Clear Wake on LAN output
Wake on LAN Output Stretch:
If WoL out is configured for pulse mode, the pulse length is defined
as the following number of 125MHz clock cycles:
11 = 64 clock cycles
10 = 32 clock cycles
01 = 16 clock cycles
00 = 8 clock cycles
Wake on LAN Output Mode:
1 = Level Mode. WoL is cleared by a write to WOL_OUT_CLEAR
(bit 11).
0 = Pulse Mode. Pulse width is configured via
WOL_OUT_STRETCH (bits 10:9).
Enable Enhanced Receive Features:
1 = Enable for Wake on LAN, CRC check, and Receive 1588
indication.
0 = Normal operation.
RESERVED
Enable SecureOn Password:
1 = SecureOn Password enabled.
0 = SecureOn Password disabled.
Wake on Unicast Packet:
1 = Issue an interrupt upon reception of Unicast packet.
0 = Do not issue an interrupt upon reception of Unicast packet.
RESERVED
Wake on Broadcast Packet:
1 = Issue an interrupt upon reception of Broadcast packet.
0 = Do not issue an interrupt upon reception of Broadcast packet.
Wake on Pattern Match:
1 = Issue an interrupt upon pattern match.
0 = Do not issue an interrupt upon pattern match.
Wake on Magic Packet:
1 = Issue an interrupt upon reception of Magic packet.
0 = Do not issue an interrupt upon reception of Magic packet.
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