DP83867IR Datasheet, PDF (20/130 Pages) Texas Instruments – High Immunity 10/100/1000 Ethernet Physical Layer Transceiver

DP83867IR, DP83867CR
SNLS484C – FEBRUARY 2015 – REVISED NOVEMBER 2015
8.10
T1
T2
T3
T4
T5
T6
GMII Transmit Timing⁽¹⁾
PARAMETER
TEST CONDITIONS
GTX_CLK Duty Cycle
GTX_CLK Rise / Fall Time
Setup from valid TXD, TX_EN
and TX_ER to rising edge of
GTX_CLK
Hold from rising edge of
GTX_CLK to invalid TXD,
TX_EN, and TX_ER
GTX_CLK Stability
GMII to MDI Latency
See ⁽²⁾
(1) Ensured by production test, characterization, or design.
(2) Operating in 1000Base-T .
tT5t
MIN
40
2
0.5
-100
GTX_CLK
T2
TXD [7:0]
TX_EN
TX_ER
T3
MDI
T4
tT6t
Figure 6. GMII Transmit Timing
NOM
72
tT1t
www.ti.com
MAX
60
1
UNIT
%
ns
ns
ns
100 ppm
ns
T2
Start of Frame
20
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