TMS320TCI6618 Datasheet, PDF (91/223 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

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4.3 TeraNet Switch Fabric Connections
TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688D—March 2012
The figures below show the connections between masters and slaves through various sections of the TeraNet.
Figure 4-1 TeraNet 3A
Bridge_1
Bridge_2
Bridge_3
From TeraNet_2_A
Bridge_4
PCIe
M
SRIO_M _M
SRIO
Packet DMA
M
TNet_3_F
CPU/3
Tracer_L2_0
Tracer_L2_1
Tracer_L2_2
Tracer_L2_3
Tracer_TAC
Tracer_QM_M
MPU_1
S ^CorePac_0
S ^CorePac_1
S ^CorePac_2
S ^CorePac_3
S ^TAC_BE
S ^QM_SS
S ^TCP3e_r
S ^TCP3e_w
S
PCIe
S ^VCP2
NETCP _M
QM_SS
Packet DMA
M
QM_SS
Second
M
Debug_SS _M
FFTC_B
Packet DMA
M
FFTC_A
Packet DMA
M
RAC_A_BE1 _M
RAC_A_BE0 _M
RAC_B_BE1 _M
RAC_B_BE0 _M
TAC_FE _M
AIF/DMA _M
TC_0 _M
EDMA ^TC_1 M
CC1 TC_2 _M
TC_3 _M
TC_0 _M
EDMA ^TC_1 M
CC2 TC_2 _M
TC_3 _M
TNet_3_H
CPU/3
TNet_3_D
CPU/3
TNet_3_B
CPU/3
Tracer
_RAC
TNet_3_G
CPU/3
TNet_3_E
CPU/3
TNet_6P_A
CPU/3
S ^VCP2
S ^VCP2
S ^VCP2
S
SRIO
S ^RAC_A_FE
S ^RAC_B_FE
S ^TCP3d_A
S ^TCP3d_B
S
SPI
S ^Boot_ROM
Bridge_5
Bridge_6
To TeraNet_2_A
Bridge_7
Bridge_8
Bridge_9
Bridge_10
To TeraNet_3P_A
Bridge_12
Bridge_13
Bridge_14
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System Interconnect 91