TMS320TCI6618 Datasheet, PDF (13/223 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

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1 TMS320TCI6618 Features
• Four TMS320C66x™ DSP Core Subsystems, Each With
– 1.0-GHz or 1.2-GHz C66x Fixed/Floating-Point
DSP Core
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 2048KB MSM SRAM Memory Shared by Four DSP
Cores
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Hardware Coprocessors
– Three Enhanced Coprocessors for Turbo Decoding
› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,
LTE, and WiMAX
› Supports up to 548 Mbps for LTE and up to
353 Mbps for WCDMA
› Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– One Enhanced Coprocessor for Turbo Encoding
› Supports up to 500 Mbps for LTE and WCDMA
– Four Viterbi Decoders
› Supports More Than 38 Mbps @ 40-bit Block
Size
– Two WCDMA Receive Acceleration Coprocessors
› Up to 256 Users @ 8 Fingers w/o Measurement
– WCDMA Transmit Acceleration Coprocessor
› Up to 256 Users with two Radio Links and
Diversity
– Three Fast Fourier Transform Coprocessors
› 2048 pt FFT in 4.8 μs
– Bit Rate Coprocessor
› WCDMA/HSPA+, TD-SCDMA, LTE, and WiMAX
Uplink and Downlink Bit Processing
› Includes Encoding, Rate Matching/Dematching,
Segmentation, Multiplexing, and More
› Supports Up To 914 Mbps for LTE and 405 Mbps
for WCDMA/TD-SCDMA
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688D—March 2012
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire-Speed Throughput at 1.5 M Packets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Four Rake/Search Accelerators (RSA) for
– Chip-Rate Processing for WCDMA Rel'99, HSDPA,
and HSDPA+
– Reed-Muller Decoding
• Peripherals
– Six-Lane SerDes-Based Antenna Interface (AIF2)
› Operating at up to 6.144 Gbps
› Compliant with OBSAI RP3 and CPRI Standards
for 3G / 4G (WCDMA, LTE TDD, LTE FDD,
TD-SCDMA, and WiMAX)
– Four Lanes of SRIO 2.1
› 5 GBaud Operation Per Lane
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud Per Lane
– Hyperlink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 40 Gbaud
– Gigabit Ethernet (GbE) Switch Subsystem
› Two SGMII Ports
› IEEE1588 Support
– 64-Bit DDR3 Interface with Speeds up to 1333 MHz
– UART Interface
– I²C Interface
– Sixteen GPIO pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 100°C
• Extended Temperature:
– - 40°C to 100°C
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2012 Texas Instruments Incorporated