TLC1549C_14 Datasheet, PDF (9/18 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C – DECEMBER 1992 – REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range,
V_CC = V_ref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz
EL
EZS
EFS
tconv
PARAMETER
Linearity error (see Note 6)
Zero-scale error (see Note 7)
Full-scale error (see Note 7)
Total unadjusted error (see Note 8)
Conversion time
tc
Total cycle time (access, sample, and conversion)
tv
td(I/O-DATA)
tPZH, tPZL
tPHZ, tPLZ
tr(bus)
tf(bus)
td(I/O-CS)
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Enable time, CS↓ to DATA OUT (MSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, data bus
Fall time, data bus
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
TEST CONDITIONS
See Note 2
See Note 2
See Figures 6 – 10
See Figures 6 – 10,
See Note 9
See Figure 5
See Figure 5
See Figure 3
See Figure 3
See Figure 5
See Figure 5
MIN MAX
±1
±1
±1
±1
21
21
+ 10 I/O
CLOCK
periods
10
240
1.3
180
300
300
UNIT
LSB
LSB
LSB
LSB
µs
µs
ns
ns
µs
ns
ns
ns
9 µs
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (Vref ₊ – Vref _–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A / D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425 µs) after the transition.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9