TLC1549C_14 Datasheet, PDF (11/18 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C – DECEMBER 1992 – REVISED MARCH 1995
CS
(see Note A)
I/O
CLOCK
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ₁
2
3
4
5
6
7
8
9
10
1
Sample Cycle B
DATA
OUT
A9
A8
MSB
Initialize
A7 A6 A5 A4 A3 A2 A1 A0
Previous Conversion Data
LSB
Figure 6. Timing for 10-Clock Transfer Using CS
Hi-Z State
B9
A/D
Conversion
Interval
(≤ 21 µs) ^Initialize
CS
(see Note A)
Must Be High on Power Up
I/O
CLOCK
1
2
3
4
5
6
7
8
9
10
Sample Cycle B
1
See Note C
DATA
OUT
A9
MSB
Initialize
A8 A7 A6 A5 A4 A3 A2 A1 A0
Low Level
B9
Previous Conversion Data
LSB
A/D Conversion
Interval
(≤ 21 µs) Initialize
Figure 7. Timing for 10-Clock Transfer Not Using CS
CS
(see Note A)
ÏÏÏÏ^{See Note B}
I/O
CLOCK
1
2
3
4
5
6
7
8
Sample Cycle B
ÎÎÎÎ ⁹
10
11 16
1
DATA
OUT
A9
A8
A7
A6
A5
A4
A3
A2
A1
Low
A0 ^Level
Hi-Z
ÎÎÎÎÎÎ _A/D
B9
MSB
Initialize
Previous Conversion Data
LSB
Conversion
Interval
(≤ 21 µs) Initialize
Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS ↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.
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