TLC0820A Datasheet, PDF (9/15 Pages) Texas Instruments – Advanced LinCMOSE HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL CONVERTERS USING MODIFIED FLASH TECHNIQUES

TLC0820AC, TLC0820AI
Advanced LinCMOS™ HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
PRINCIPLES OF OPERATION
The TLC0820AC and TLC0820AI each employ a combination of sampled-data comparator techniques and flash
techniques common to many high-speed converters. Two 4-bit flash analog-to-digital conversions are used to give
a full 8-bit output.
The recommended analog input voltage range for conversion is – 0.1 V to V_CC + 0.1 V. Analog input signals that are
less than V_{ref –} + 1/2 LSB or greater than V_ref+ – 1/2 LSB convert to 00000000 or 11111111, respectively. The reference
inputs are fully differential with common-mode limits defined by the supply rails. The reference input values define
the full-scale range of the analog input. This allows the gain of the ADC to be varied for ratiometric conversion by
changing the V_ref+ and V_{ref –} voltages.
The device operates in two modes, read (only) and write-read, that are selected by MODE. The converter is set to
the read (only) mode when MODE is low. In the read mode, WR/RDY is used as an output and is referred to as the
ready terminal. In this mode, a low on WR/RDY while CS is low indicates that the device is busy. Conversion starts
on the falling edge of RD and is completed no more than 2.5 µs later when INT falls and WR/RDY returns to the
high-impedance state. Data outputs also change from high-impedance to active states at this time. After the data is
read, RD is taken high, INT returns high, and the data outputs return to their high-impedance states.
When MODE is high, the converter is set to the write-read mode and WR/RDY is referred to as the write terminal.
Taking CS and WR/RDY low selects the converter and initiates measurement of the input signal. Approximately
600 ns after WR/RDY returns high, the conversion is completed. Conversion starts on the rising edge of WR/RDY
in the write-read mode.
The high-order 4-bit flash ADC measures the input by means of 16 comparators operating simultaneously. A
high-precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After a time
delay, a second bank of comparators does a low-order conversion on the analog difference between the input level
and the high-order DAC output. The results from each of these conversions enter an 8-bit latch and are output to the
3-state output buffers on the falling edge of RD.
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