SN74LVC1G74_16 Datasheet, PDF (9/24 Pages) Texas Instruments – SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

www.ti.com
9 Detailed Description
SN74LVC1G74
SCES794E – OCTOBER 2009 – REVISED JANUARY 2015
9.1 Overview
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
PRE ⁷
CLK ¹
C
C
C
TG
5
Q
C
C
D2
TG
TG
C
C
TG
C
C
C
CLR ⁶
9.3 Feature Description
• Allow down voltage translation
– 5 V to 3.3 V
– 5.0 V to 1.8 V
– 3.3 V to 1.8 V
• Inputs accept voltage levels up to 5.5 V
• I_off Feature
– Can prevent backflow current that can damage device when powered down
9.4 Device Functional Modes
Table 1. Function Table
PRE
L
H
L
H
H
H
INPUTS
CLR
CLK
D
H
X
X
L
X
X
L
X
X
H
↑
H
H
↑
L
H
L
X
OUTPUTS
Q
H
L
H ⁽¹⁾
H
L
Q₀
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
3Q
Q
L
H
H ⁽¹⁾
L
H
Q₀
Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G74
Submit Documentation Feedback
9