SN74LVC1G00_16 Datasheet, PDF (9/36 Pages) Texas Instruments – SN74LVC1G00_16

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9 Detailed Description
SN74LVC1G00
SCES212AB – APRIL 1999 – REVISED APRIL 2014
9.1 Overview
The SN74LVC1G00 device contains one 2-input positive-NAND gate and performs the Boolean function
Y = A × B or Y = A + B. This device is fully specified for partial-power-down applications using I_off. The I_off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
9.2 Functional Block Diagram
9.3 Feature Description
• Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
• Allows down voltage translation.
• Inputs accept voltages to 5.5 V.
• I_off feature allows voltages on the inputs and outputs, when V_CC is 0 V.
9.4 Device Functional Modes
Function Table
INPUTS
A
B
H
H
L
X
X
L
OUTPUT
Y
L
H
H
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