MSP430F249-EP_014 Datasheet, PDF (9/81 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F249-EP
MIXED SIGNAL MICROCONTROLLER
2008
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out of range (see Note 1)
PORIFG
WDTIFG
RSTIFG
KEYV
(see Note 2)
Reset
0xFFFE
31, highest
NMI
NMIIFG
(Non)maskable
0xFFFC
Oscillator fault
OFIFG
(Non)maskable
30
Flash memory access violation ACCVIFG (see Notes 2 and 7)
(Non)maskable
Timer_B7 (see Note 3)
TBCCR0 CCIFG
(see Note 4)
Maskable
0xFFFA
29
Timer_B7 (see Note 3)
TBCCR1 to TBCCR6 CCIFGs,
TBIFG (see Notes 2 and 4)
Maskable
0xFFF8
28
Comparator_A+
CAIFG
Maskable
0xFFF6
27
Watchdog timer+
WDTIFG
Maskable
0xFFF4
26
Timer_A3
TACCR0 CCIFG (see Note 4)
Maskable
0xFFF2
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Note 2 and 4)
Maskable
0xFFF0
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Note 2 and 5)
Maskable
0xFFEE
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive / transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 6)
Maskable
0xFFEC
22
ADC12 (see Note 8)
ADC12IFG
(see Notes 2 and 4)
Maskable
0xFFEA
21
0xFFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 and 4)
Maskable
0xFFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 4)
Maskable
0xFFE4
18
USCI A1/B1 receive
UCA1RXIFG, UCB1RXIFG
(see Note 2)
Maskable
0xFFE2
17
USCI A1/B1 transmit
UCA1TXIFG, UCB1TXIFG
(see Note 2)
Maskable
0xFFE0
16
Reserved (see Notes 9 and 10)
Reserved
0xFFDE to 0xFFC0 15 to 0, lowest
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 −0x01FF)
or from within unused address ranges.
2. Multiple source flags.
3. Timer_B7 in MSP430F24x(1), MSP430F2410 family has 7 CCRs, Timer_B3 in MSP430F23x family has three CCRs. In Timer_B3,
there are only interrupt flags TBCCR0, 1, and 2 CCIFGs, and the interrupt enable bits TBCCTL0, 1, and 2 CCIE.
4. Interrupt flags are located in the module.
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
7. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
8. ADC12 is not implemented in the MSP430F24x1 family.
9. The address 0xFFDE is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
10. The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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