MSP430F21X2_17 Datasheet, PDF(9/80 Page) Texas Instruments

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MSP430F21X2_17 Datasheet, PDF (9/80 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

◁

MSP430F21x2

www.ti.com

SLAS578J â NOVEMBER 2007 â REVISED JANUARY 2012

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (for example, if flash is not programmed), the

CPU goes into LPM4 immediately after power up.

Table 5. Interrupt Vector Addresses

INTERRUPT SOURCE

Power-up

External reset

Watchdog

Flash key violation

PC out of range(2)

NMI

Oscillator fault

Flash memory access violation

Timer1_A2

Comparator_A+

Watchdog timer

Timer0_A3

USCI_A0/USCI_B0 receive

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit

USCI_B0 I2C receive/transmit

ADC10

I/O port P2 (eight flags)

I/O port P1 (eight flags)

See (7)

See (8)

INTERRUPT FLAG

PORIFG

RSTIFG

WDTIFG

KEYV (1)

NMIIFG

OFIFG

ACCVIFG (1) (3)

TA1CCR0 CCIFG(4)

TA1CCR1 CCIFG,

TA1CTL TAIFG(1)(4)

CAIFG

WDTIFG

TA0CCR0 CCIFG(4)

TA0CCR1 CCIFG,

TA0CCR2 CCIFG,

TA0CTL TAIFG(1)(4)

UCA0RXIFG,

UCB0RXIFG (1) (5)

UCA0TXIFG,

UCB0TXIFG (1) (6)

ADC10IFG (4)

P2IFG.0 to P2IFG.7(1)(4)

P1IFG.0 to P1IFG.7(1)(4)

SYSTEM INTERRUPT

Reset

(Non)maskable

Maskable

WORD ADDRESS

PRIORITY

0xFFFE

31, highest

0xFFFC

0xFFFA

0xFFF8

0xFFF6

0xFFF4

0xFFF2

0xFFF0

0xFFEE

0xFFEC

0xFFEA

0xFFE8

0xFFE6

0xFFE4

0xFFE2

0xFFE0

0xFFDE

0xFFDC to 0xFFC0

14 to 0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or

from within unused address range.

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

(4) Interrupt flags are located in the module.

(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG

(6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG

(7) This location is used as bootstrap loader security key (BSLSKEY).

A 0xAA55 at this location disables the BSL completely.

A zero (0x0) disables the erasure of the flash if an invalid password is supplied.

(8) The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if

necessary.

Submit Documentation Feedback

▷