MSP430AFE2X3_17 Datasheet, PDF (9/50 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430AFE2x3
MSP430AFE2x2
MSP430AFE2x1
SLAS701A – NOVEMBER 2010 – REVISED MARCH 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
INTERRUPT SOURCE
Power up
External reset
Watchdog
Flash key violation
PC out-of-range⁽¹⁾
NMI
Oscillator fault
Flash memory access violation
SD24_A
Watchdog Timer
USART0 Receive
USART0 Transmit
Timer_A3
Timer_A3
I/O Port P1 (eight flags)
I/O Port P2 (three flags)
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(2)
NMIIFG
OFIFG
ACCVIFG ^{(2) (3)}
SD24CCTLx SD24OVIFG,
SD24CCTLx SD24IFG^{(2) (4)}
WDTIFG
URXIFG0
UTXIFG0
TA0CCR0 CCIFG⁽⁴⁾
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG ^{(2) (4)}
P1IFG.0 to P1IFG.7^{(2) (4)}
P2IFG.0 to P2IFG.2^{(2) (4)}
SYSTEM
INTERRUPT
WORD ADDRESS
Reset
0FFFEh
(Non)maskable,
(Non)maskable,
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
PRIORITY
15, highest
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
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