LMD18200QML Datasheet, PDF (9/18 Pages) Texas Instruments – 2.4A, 55V H-Bridge

PWM
H
H
L
H
H
L
TABLE 1. Logic Truth Table
Dir
Brake
Active Output Drivers
H
L Source 1, Sink 2
L
L Sink 1, Source 2
X
L Source 1, Source 2
H
H Source 1, Source 2
L
H Sink 1, Sink 2
X
H None
Application Information
TYPES OF PWM SIGNALS
The LMD18200 readily interfaces with different forms of PWM
signals. Use of the part with two of the more popular forms of
PWM is described in the following paragraphs.
Simple, locked anti-phase PWM consists of a single, vari-
able duty-cycle signal in which is encoded both direction and
amplitude information (see Figure 2). A 50% duty-cycle PWM
signal represents zero drive, since the net value of voltage
(integrated over one period) delivered to the load is zero. For
the LMD18200, the PWM signal drives the direction input (pin
3) and the PWM input (pin 5) is tied to logic high.
Sign/magnitude PWM consists of separate direction (sign)
and amplitude (magnitude) signals (see Figure 3). The (ab-
solute) magnitude signal is duty-cycle modulated, and the
absence of a pulse signal (a continuous logic low level) rep-
resents zero drive. Current delivered to the load is propor-
tional to pulse width. For the LMD18200, the DIRECTION
input (pin 3) is driven by the sign signal and the PWM input
(pin 5) is driven by the magnitude signal.
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FIGURE 3. Sign/Magnitude PWM Control
SIGNAL TRANSITION REQUIREMENTS
To ensure proper internal logic performance, it is good prac-
tice to avoid aligning the falling and rising edges of input
signals. A delay of at least 1 µsec should be incorporated be-
tween transitions of the Direction, Brake, and/or PWM input
signals. A conservative approach is be sure there is at least
500ns delay between the end of the first transition and the
beginning of the second transition. See Figure 4.
20160904
FIGURE 2. Locked Anti-Phase PWM Control
20160924
FIGURE 4. Transitions in Brake, Direction, or PWM Must Be Separated By At Least 1 µsec
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