DS90LV049Q Datasheet, PDF (9/14 Pages) Texas Instruments – DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair

Applications Information
General application guidelines and hints for LVDS drivers and
receivers may be found in the following application notes:
LVDS Owner's Manual (lit #550062-003), AN-805, AN-808,
AN-903, AN-916, AN-971, AN-977.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 10. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The receiv-
er is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic differential
impedance of the media is in the range of 100 Ω. A termination
resistor of 100 Ω (selected to match the media), and is located
as close to the receiver input pins as possible. The termination
resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and other
impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be taken into
account.
The TRI-STATE function allows the device outputs to be dis-
abled, thus obtaining an even lower power state when the
transmission of data is not required.
The DS90LV049Q has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the device
easily allows for matching electrical lengths of the differential
pair trace lines between the driver and the receiver as well as
allowing the trace lines to be close together to couple noise
as common-mode. Noise isolation is achieved with the LVDS
signals on one side of the device and the TTL signals on the
other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high fre-
quency ceramic (surface mount is recommended) 0.1 μF and
0.001 μF capacitors in parallel at the power supply pin with
the smallest value capacitor closest to the device supply pin.
Additional scattered capacitors over the printed circuit board
will improve decoupling. Multiple vias should be used to con-
nect the decoupling capacitors to the power planes. A 10 μF
(35 V) or greater solid tantalum capacitor should be connect-
ed at the power entry point on the printed circuit board be-
tween the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a pow-
er/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential
impedance of your transmission medium (i.e. cable) and ter-
mination resistor. Run the differential pair trace lines as close
together as possible as soon as they leave the IC (stubs
should be < 10 mm long). This will help eliminate reflections
and ensure noise is coupled as common-mode. In fact, we
have seen that differential signals which are 1 mm apart ra-
diate far less noise than traces 3 mm apart since magnetic
field cancellation is much better with the closer traces. In ad-
dition, noise induced on the differential lines is much more
likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference
between signals which destroys the magnetic field cancella-
tion benefits of differential signals and EMI will result. (Note
the velocity of propagation, v = c/Er where c (the speed of
light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on
the autoroute function for differential traces. Carefully review
dimensions to match differential impedance and provide iso-
lation for the differential lines. Minimize the number or vias
and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use
arcs or 45° bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
TERMINATION
Use a termination resistor which best matches the differential
impedance or your transmission line. The resistor should be
between 90 Ω and 130 Ω. Remember that the current mode
outputs need the termination resistor to generate the differ-
ential voltage. LVDS will not work without resistor termination.
Typically, connecting a single resistor across the pair at the
receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, com-
ponent lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10 mm
(12 mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100 kΩ), low capacitance
(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.
Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important
to remember:
Use controlled impedance media. The cables and connectors
you use should have a matched differential impedance of
about 100 Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differential
mode) noise which is rejected by the receiver.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that am-
plifies a small differential signal (20 mV) to CMOS logic levels.
Due to the high gain and tight threshold of the receiver, care
should be taken to prevent noise from appearing as a valid
signal.
The receiver's internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection
(a stable known state of HIGH output voltage) for floating re-
ceiver inputs.
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