DP83630 Datasheet, PDF (9/128 Pages) Texas Instruments – DP83630 Precision PHYTER - IEEE® 1588 Precision Time Protocol Transceiver

6.1.2 IEEE 1588 Clock Input
The IEEE 1588 PTP logic operates on a nominal 125 MHz
reference clock generated by an internal Phase Generation
Module (PGM). However, options are available to use a di-
vided-down version of the PGM clock to reduce power con-
sumption at the expense of precision, or to use an external
reference clock of up to 125 MHz in the event the 1588 clock
is tracked externally.
6.2 PACKET TIMESTAMPS
6.2.1 IEEE 1588 Transmit Packet Parser and Timestamp
The IEEE 1588 transmit parser monitors transmit packet data
to detect IEEE 1588 Version 1 and Version 2 Event mes-
sages. The transmit parser can detect PTP Event messages
transported directly in Layer2 Ethernet packets as well as in
UDP/IPv4 and UDP/IPv6 packets. Upon detection of a PTP
Event Message, the device will capture the transmit times-
tamp and provide it to software.
Since software knows the order of packet transmission, only
the timestamp is recorded (there is no need to record se-
quence number or other information). The device can buffer
four timestamps.
If enabled, an interrupt may be generated upon a Transmit
Timestamp Ready.
6.2.1.1 One-Step Operation
In some cases, the transmitter can be set to operate in a One-
Step mode. For Sync Messages, a One-Step device can
automatically insert timestamp information in the outgoing
packet. This eliminates the need for software to read the
timestamp and send a follow up message.
6.2.2 IEEE 1588 Receive Packet Parser and Timestamp
The IEEE 1588 receive parser monitors receive packet data
to detect IEEE 1588 Version 1 and Version 2 Event mes-
sages. The receive parser can detect PTP Event messages
transported directly in Ethernet packets as well as in UDP/
IPv4 and UDP/IPv6 packets. Upon detection of a PTP Event
message, the device will capture the receive timestamp and
provide the timestamp value to software. In addition to the
timestamp, the device will record the 16-bit SequenceId, the
4-bit messageType field, and generate a 12-bit hash value for
octets 20-29 of the PTP event message. The device can
buffer four timestamps.
An interrupt will be generated, if enabled, upon a Receive
Timestamp Ready.
6.2.2.1 Receive Timestamp Insertion
The DP83630 can deliver the timestamp to software by in-
serting the timestamp in the received packet. This allows for
a simple method to deliver the packet to software without
having to match the timestamp to the correct packet. This also
eliminates the need to read the receive timestamp through the
Serial Management Interface.
6.2.3 NTP Packet Timestamp
The DP83630 may be programmed to timestamp NTP pack-
ets instead of PTP packets. This operation is enabled by
setting the NTP_TS_EN control in the PTP_TXCFG0 register.
When configured for NTP timestamps, the DP83630 will
timestamp packets with the NTP UDP port number rather than
the PTP port number (note that the device cannot be config-
ured to timestamp both PTP and NTP packets). One-Step
operation is not supported for NTP timestamps, so transmit
timestamps cannot be inserted directly into outgoing NTP
packets. Timestamp insertion is available for receive times-
tamps but must use a single, fixed location.
6.3 EVENT TRIGGERING AND TIMESTAMPING
6.3.1 IEEE 1588 Event Triggering
The DP83630 is capable of being programmed to generate a
trigger signal on an output pin based on the IEEE 1588 time
value. Each trigger can be programmed to generate a one-
time rising or falling edge, a single pulse of programmable
width, or a periodic signal.
For each trigger, the microcontroller specifies the desired
GPIO and time that the activity is to occur. The trigger is gen-
erated when the internal IEEE 1588 clock matches the de-
sired activation time.
The device supports up to 8 trigger signals which can be out-
put on any of the GPIO signal pins. Multiple triggers may be
assigned to a single GPIO, allowing generation of more com-
plex waveforms (i.e. a sequence of varying width pulses). The
trigger signals are OR’ed together to form a combined signal.
The triggers are configured through the PTP Trigger Config-
uration Registers. The trigger time and width settings are
controlled through the PTP Control and Time Data registers.
The DP83630 can be programmed to output a Pulse-Per-
Second (PPS) signal using the trigger functions.
6.3.2 IEEE 1588 Event Timestamping
The DP83630 can be programmed to timestamp an event by
monitoring an input signal. The event can be monitored for
rising edge, falling edge, or either. The Event Timestamp Unit
can monitor up to eight events which can be set to any of the
GPIO signal pins. PTP event timestamps are stored in a
queue which allows storage of up to eight timestamps.
When an event timestamp is available, the device will set the
EVENT_RDY bit in the PTP Status Register. The PTP Event
Status Register (PTP_ESTS) provides detailed information
on the next available event timestamp, including information
on the event number, rise/fall direction, and indication of
events missed due to overflow of the devices Event queue.
Event timestamp values should be adjusted by 35 ns (3 times
period of the IEEE 1588 reference clock frequency of 125
MHz + 11 ns) to compensate for input path and synchroniza-
tion delays.
The Event Timestamp Unit is configured through the PTP
Event Configuration Register (PTP_EVNT).
6.4 PTP INTERRUPTS
The PTP module may interrupt the system using the PWR-
DOWN/INTN pin on the device, shared with other interrupts
from the PHY. As an alternative, the device may be pro-
grammed to use a GPIO pin to generate PTP interrupts
separate from other PHY interrupts.
6.5 GPIO
The DP83630 features 12 IEEE 1588 GPIO pins. These GPIO
pins allow for event monitoring, triggering, interrupts, and a
clock output. The LED pins comprise 3 of the 12 GPIO pins.
If an LED pin is to be used as a GPIO, its LED function must
be disabled prior to configuring the GPIO function.
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