DP83630 Datasheet, PDF (35/128 Pages) Texas Instruments – DP83630 Precision PHYTER - IEEE® 1588 Precision Time Protocol Transceiver

11.3.3 Far-End Fault
Since 100BASE-FX does not support Auto-Negotiation, a
Far-End Fault facility is included which allows for detection of
link failures.
When no signal is being received as determined by the Signal
Detect function, the device sends a Far-End Fault indication
to the far-end peer. The Far-End Fault indication is comprised
of 3 or more repeating cycles, each consisting of 84 one’s
followed by 1 zero. The pattern is such that it will not satisfy
the 100BASE-X carrier sense mechanism, but is easily de-
tected as the Fault indication. The pattern will be transparent
to devices that do not support Far-End Fault.
The Far-End Fault detection process continuously monitors
the receive data stream for the Far-End Fault indication.
When detected, the Link Monitor is forced to deassert Link
status. This causes the device to transmit IDLE’s on its trans-
mit path.
11.4 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compliant.
It includes the receiver, transmitter, collision, heartbeat, loop-
back, jabber, and link integrity functions, as defined in the
standard. An external filter is not required on the 10BASE-T
interface since this is integrated inside the DP83630. This
section focuses on the general 10BASE-T system level op-
eration.
11.4.1 Operational Modes
The DP83630 has two basic 10BASE-T operational modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83630 functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD
protocol.
Full Duplex Mode
In Full Duplex mode the DP83630 is capable of simultane-
ously transmitting and receiving without asserting the collision
signal. The DP83630's 10 Mb/s ENDEC is designed to en-
code and decode simultaneously.
11.4.2 Smart Squelch
The smart squelch is responsible for determining when valid
data is present on the differential receive inputs. The
DP83630 implements an intelligent receive squelch to ensure
that impulse noise on the receive inputs will not be mistaken
for a valid signal. Smart squelch operation is independent of
the 10BASE-T operational mode.
The squelch circuitry employs a combination of amplitude and
timing measurements (as specified in the IEEE 802.3
10BASE-T standard) to determine the validity of data on the
twisted pair inputs (refer to Figure 8).
The signal at the start of a packet is checked by the smart
squelch and any pulses not exceeding the squelch level (ei-
ther positive or negative, depending upon polarity) will be
rejected. Once this first squelch level is overcome correctly,
the opposite squelch level must then be exceeded within 150
ns. Finally the signal must again exceed the original squelch
level within 150 ns to ensure that the input waveform will not
be rejected. This checking procedure results in the loss of
typically three preamble bits at the beginning of each packet.
Only after all these conditions have been satisfied will a con-
trol signal be generated to indicate to the remainder of the
circuitry that valid data is present. At this time, the smart
squelch circuitry is reset.
Valid data is considered to be present until the squelch level
has not been generated for a time longer than 150 ns, indi-
cating the End of Packet. Once good data has been detected,
the squelch levels are reduced to minimize the effect of noise
causing premature End of Packet detection.
The receive squelch threshold level can be lowered for use in
longer cable or STP applications. This is achieved by config-
uring the SQUELCH bits (11:9) in the 10BTSCR register
(0x1A).
FIGURE 8. 10BASE-T Twisted Pair Smart Squelch Operation
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11.4.3 Collision Detection and SQE
When in Half Duplex, a 10BASE-T collision is detected when
the receive and transmit channels are active simultaneously.
Collisions are reported by the COL signal on the MII. Colli-
sions are also reported when a jabber condition is detected.
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