CDCEL824 Datasheet, PDF (9/33 Pages) Texas Instruments – Programmable 2-PLL Clock Synthesizer

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9 Detailed Description
CDCEL824
SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015
9.1 Overview
The CDCEL824 is a modular PLL-based low-cost, high-performance, programmable clock synthesizer, multiplier,
and divider. It generates up to four output clocks from a single input frequency. Each output can be programmed
in-system for any clock frequency up to 201 MHz, using up to two independent configurable PLLs.
The CDCEL824 has a separate output supply pins, V_DDOUT, which are 1.8 V.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from a 27-MHz reference input frequency, for
example.
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It
is preset to a factory default configuration and can be reprogrammed to a different application configuration
before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable
through the SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or other
control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so
forth.
The CDCx824 operates in a 1.8-V environment. It operates in a temperature range of –40°C to 85°C.
9.2 Functional Block Diagram
Vctr
Xin/CLK
Xout
S0
S1/SDA
S2/SCL
VCXO
XO
LVCMOS
EEPROM
Programming
and
SDA/SCL
Register
V _DD
PLL 1
PLL Bypass
PLL 2
GND
Pdiv2
7-Bit
Pdiv3
7-Bit
Pdiv4
7-Bit
V _DDOUT
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
PLL Bypass
Pdiv5
7-Bit
LV
CMOS
Y4
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: CDCEL824
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