CDCEL824 Datasheet, PDF (1/33 Pages) Texas Instruments – Programmable 2-PLL Clock Synthesizer

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CDCEL824
SCAS945A – JUNE 2015 – REVISED SEPTEMBER 2015
CDCEL824 Programmable 2-PLL Clock Synthesizer
1 Features
•1 Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2]: for example, Frequency Switching,
Output Enable, or Power Down
– Enables 0-PPM Clock Generation
• In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
• Flexible Input Clocking Concept
– External Crystal: 20 MHz to 30 MHz
– Single-Ended LVCMOS up to 130 MHz
• Selectable Output Frequency up to 201 MHz
• Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 80 ps)
• 1.8-V Device Power Supply
• Temperature Range –40°C to 85°C
• Packaged in TSSOP
2 Applications
Laser Distance Measurement Applications
3 Description
The CDCEL824 is a modular PLL-based low-cost,
high-performance, programmable clock synthesizer,
multiplier, and divider. It generates up to four output
clocks from a single input frequency. Each output can
be programmed in-system for any clock frequency up
to 201 MHz, using up to two independent
configurable PLLs.
The CDCEL824 has a separate output supply pins,
V_DDOUT, which are 1.8 V.
The input accepts an external crystal or LVCMOS
clock signal. In case of a crystal input, an on-chip
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from
0 pF to 20 pF.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCEL824
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Schematic
Ethernet PHY
CDCEL824
WiFi
USB Controller
25 MHz
FPGA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.