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BQ24735 Datasheet, PDF (9/42 Pages) Texas Instruments – 1-4 Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode with N-Channel Power MOSFET Selector
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bq24735
SLUSAK9 – SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ANALOG INPUT (ACDET, ILIM)
IIN_ LEAK
Input bias current
PWM OSCILLATOR
V=7V
–1
1
FSW
PWM switching frequency
FSW+
PWM increase frequency
FSW–
PWM decrease frequency
BATFET GATE DRIVER (BATDRV)
ChargeOption () bit [9] = 0 (Default)
ChargeOption() bit [10:9] = 11
ChargeOption() bit [10:9] = 01
600
750
900
665
885 1100
465
615
765
IBATFET
VBATFET
RBATDRV_LOAD
BATDRV charge pump current limit
Gate drive voltage on BATFET
Minimum load resistance between
BATDRV and SRN
VBATDRV - VSRN when VSRN > UVLO
40
60
5.5
6.1
6.5
500
RBATDRV_OFF
BATDRV turn-off resistance
ACFET GATE DRIVER (ACDRV)
I = 30 µA
5
6.2
7.4
IACFET
VACFET
RACDRV_LOAD
ACDRV charge pump current limit
Gate drive voltage on ACFET
Minimum load resistance between ACDRV
and CMSRC
VACDRV–VCMSRC when VVCC> UVLO
40
60
5.5
6.1
6.5
500
RACDRV_OFF
VACFET_LOW
ACDRV turn-off resistance
ACDRV Turn-Off when Vgs voltage is low
(Specified by design)
I = 30 µA
5
6.2
7.4
5.9
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver turn-on resistance
VBTST – VPH = 5.5 V, I = 10 mA
6
10
RDS_HI_OFF
High side driver turn-off resistance
VBTST – VPH = 5.5 V, I = 10 mA
0.65
1.3
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh pulse is requested
3.85
4.3
4.7
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver turn-on resistance
RDS_LO_OFF
Low side driver turn-off resistance
PWM DRIVER TIMING
VREGN = 6 V, I = 10 mA
VREGN = 6 V, I = 10 mA
7.5
12
0.9
1.4
tLOW_HIGH
Driver dead time from low side to high side
20
tHIGH_LOW
Driver dead time from high side to low side
20
INTERNAL SOFT START
ISTEP
Soft start current step
In CCM mode 10mΩ current sensing resistor
64
tSTEP
Soft start current step time
240
SMBus TIMING CHARACTERISTICS
tR
tF
tW(H)
tW(L)
tSU(STA)
tH(STA)
tSU(DAT)
tH(DAT)
tSU(STOP)
t(BUF)
FS(CL)
SCLK/SDATA rise time
SCLK/SDATA fall time
SCLK pulse width high
SCLK Pulse Width Low
Setup time for START condition
START condition hold time after which first clock pulse is generated
Data setup time
Data hold time
Setup time for STOP condition
Bus free time between START and STOP condition
Clock Frequency
1
300
4
50
4.7
4.7
4
250
300
4
4.7
10
100
UNIT
μA
kHz
kHz
kHz
µA
V
kΩ
kΩ
μA
V
kΩ
kΩ
V
Ω
Ω
V
Ω
Ω
ns
ns
mA
μs
μs
ns
μs
μs
μs
μs
ns
ns
µs
μs
kHz
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