BQ2010_15 Datasheet, PDF (9/26 Pages) Texas Instruments – Gas Gauge IC

Not Recommended For New Designs
bq2010
Table 5. bq2010 Current-Sensing Errors
Symbol
Parameter
V_OS
Offset referred to V_SR
INL
Integrated non-linearity
error
INR
Integrated non-
repeatability error
Typical
± 50
±2
±1
Maximum
± 150
±4
±2
Units
µV
%
%
Notes
DISP = V_CC.
Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.
Measurement repeatability given
similar operating conditions.
the bq2010 should be pulled up by the host system or may
be left floating if the serial interface is not used.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2010.
The command directs the bq2010 either to store the next
eight bits of data received to a register specified by the
command byte or to output the eight bits of data speci-
fied by the command byte.
The communication protocol is asynchronous return-to-
one. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using
either polled or interrupt processing. Data input from the
bq2010 may be sampled using the pulse-width capture
timers available on some microcontrollers.
Communication is normally initiated by the host processor
sending a BREAK command to the bq2010. A BREAK is
detected when the DQ pin is driven to a logic-low state for
a time, t_B or greater. The DQ pin should then be returned
to its normal ready-high logic state for a time, t_BR. The
bq2010 is now ready to receive a command from the host
processor.
The return-to-one data bit frame consists of three distinct
sections. The first section is used to start the transmission
by either the host or the bq2010 taking the DQ pin to a
logic-low state for a period, t_STRH,B. The next section is the
actual data transmission, where the data should be valid
by a period, t_DSU, after the negative edge used to start
communication. The data should be held for a period,
t_DV, to allow the host or bq2010 to sample the data bit.
The final section is used to stop the transmission by re-
turning the DQ pin to a logic-high state by at least a peri-
od, t_SSU, after the negative edge used to start communica-
tion. The final logic-high state should be held until a peri-
od, t_SV, to allow time to ensure that the bit transmission
was stopped properly. The timings for data and break
communication are given in the serial communication tim-
ing specification and illustration sections.
Communication with the bq2010 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication se-
quence to read the bq2010 NAC register.
bq2010 Registers
The bq2010 command and status registers are listed in
Table 6 and described below.
Command Register (CMDR)
The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2010.
The CMDR register contains two fields:
n _{W/R bit}
n _{Command address}
The W/R bit of the command register is used to select
whether the received command is for a read or a write
function.
Written by Host to bq2010 Received by Host to bq2010
CMDR = 03h
NAC = 65h
LSB
MSB LSB
MSB
Break 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0
DQ
TD201001.eps
Figure 3. Typical Communication with the bq2010
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