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AMC7836 Datasheet, PDF (9/88 Pages) Texas Instruments – AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports
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AMC7836
SLAS986C – NOVEMBER 2014 – REVISED APRIL 2016
Electrical Characteristics: DAC (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AVDD = DVDD = 4.5 to 5.5 V, AVCC = 12 V, IOVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, AVEE =
AVSSB = AVSSC = AVSSD = –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output
range = 0 to 10 V for all groups, no load on the DACs, TA = –40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DAC OUTPUT CHARACTERISTICS
Set at power-up or reset through auto-range
–10
0
detection. The output range can be modified after
power-up or reset through the DAC range registers
(address 0x1E through 0x1F). DAC-RANGE = 100b
The output range can be modified after power-up or
–5
reset through the DAC range registers (address 0x1E
through 0x1F). DAC-RANGE = 101b
Full-scale output voltage range(2)
Set at power-up or reset through auto-range
0
detection. The output range can be modified after
power-up or reset through the DAC range registers
(address 0x1E through 0x1F). DAC-RANGE = 111b
0
V
5
The output range can be modified after power-up or
0
10
reset through the DAC range registers (address 0x1E
through 0x1F). DAC-RANGE = 110b
Output voltage settling time
Slew rate
Short circuit current
Load current(3)
Maximum capacitive load(4)
DC output impedance
Transition: Code 400h to C00h to within ½ LSB, RL =
2 kΩ, CL = 200 pF. 0 to 10 V and –10 to 0 V ranges
Transition: Code 400h to C00h to within ½ LSB, RL =
2 kΩ, CL = 200 pF. 0 to 5 V and –5 to 0 V ranges
Transition: Code 400h to C00h, 10% to 90%, RL = 2
kΩ, CL = 200 pF. 0 to 10 V and –10 to 0 V ranges
Transition: Code 400h to C00h, 10% to 90%, RL = 2
kΩ, CL = 200 pF. 0 to 5 V and –5 to 0 V ranges
Full-scale current shorted to the DAC group AVSS or
AVCC voltage
Source or sink with 1-V headroom from the DAC
group AVCC or AVSS voltage, voltage drop < 25 mV
Source or sink with 300-mV headroom from the DAC
group AVCC or AVSS voltage, voltage drop < 25 mV
RL = ∞
Code set to 800h, ±15mA
10
10
1.25
1.25
±45
±15
±10
0
1
µs
V/µs
mA
mA
10
nF
Ω
Power-on overshoot
AVEE = AVSSB = AVSSC = AVSSD = AGND, AVCC = 0
to 12 V, 2-ms ramp
10
mV
Glitch energy
Transition: Code 7FFh to 800h; 800h to 7FFh
1
nV-s
Output noise
TA = 25°C, 1 kHz, code 800h, includes internal
reference noise
TA = 25°C, integrated noise from 0.1 Hz to 10 Hz,
code 800h, includes internal reference noise
520
nV/√Hz
20
µVPP
CLAMP OUTPUTS
Clamp output voltage(5)
Clamp output impedance
DAC output range: 0 to 10 V, AVSS = AGND
DAC output range: 0 to 5 V, AVSS = AGND
DAC output range: –10 to 0 V, AVSS = –12 V
DAC output range: –5 to 0 V, AVSS = –6 V
0
0
V
AVSS + 2
AVSS + 1
8
kΩ
(2) The output voltage of each DAC group must not be greater than that of the corresponding AVCC pin (AVCC_AB or AVCC_CD) or lower than
that of the corresponding AVSS pin (AVEE, AVSSB, AVSSC or AVSSD). See the DAC Output Range and Clamp Configuration section for
more details.
(3) If all channels are simultaneously loaded, care must be taken to ensure the thermal conditions for the device are not exceeded.
(4) To be sampled during initial release to ensure compliance; not subject to production testing.
(5) No DAC load to the DAC group AVSS pin.
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