ADS6142-HT Datasheet, PDF (9/49 Pages) Texas Instruments – 14-BITS, 65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS6142-HT
SLWS234 – DECEMBER 2011
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS
differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
PARAMETER
TEST CONDITIONS
DYNAMIC AC CHARACTERISTICS
SNR
Signal-to-noise ratio,
CMOS
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
F_in = 170 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
SNR
Signal-to-noise ratio,
LVDS
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
F_in = 170 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
RMS output noise
Inputs tied to common-mode
SINAD
Signal-to-noise and
distortion ratio
CMOS
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
F_in = 170 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
SINAD
Signal-to-noise and
distortion ratio
LVDS
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
F_in = 170 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
ENOB
Effective number of bits
SFDR
Spurious free dynamic
range
F_in = 50 MHz
F_in = 70 MHz
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
F_in = 170 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
F_in = 10 MHz
F_in = 50 MHz
F_in = 70 MHz
THD
Total harmonic distortion _{Fin = 170 MHz}
0 dB Gain
3.5 dB Coarse gain
F_in = 230 MHz
0 dB Gain
3.5 dB Coarse gain
T_J = -40°C to 125°C
MIN
TYP
MAX
74.7
74.4
61.5
74.4
72.7
71.8
71.7
70.9
75
74.6
68
74.6
72.9
72.1
72
71.2
1.05
74.6
74.1
60.5
74.0
72.2
71.5
70.6
70.4
74.9
74.4
67
74.4
72.4
71.9
70.5
70.5
10.5
12
95
89
70
78
82
84
79
82
93
88
72
85
80
82
76
78.5
T_J = 210°C
MIN
TYP
MAX
UNIT
57.5
74
65.5
63
62
75
60
56.5
74
56
57
64
74
56
9.4
12
66
77
58
60
66
75
56
59
dBFS
dBFS
LSB
dBFS
dBFS
Bits
dBc
dBc
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