ADS6142-HT Datasheet, PDF (24/49 Pages) Texas Instruments – 14-BITS, 65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6142-HT
SLWS234 – DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 230 MHz INPUT SIGNAL
0
SFDR = 83 dBc
−20 ^{SINAD = 71.2 dBFS}
SNR = 71.9 dBFS
−40 ^{THD = 79.8 dBc}
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
f_IN1 = 190 MHz, –7 dBFS
f_IN2 = 185 MHz, –7 dBFS
2-Tone IMD = –88 dBFS
−40
SFDR = –92 dBFS
−60
−60
−80
−80
−100
−100
−120
−120
−140
−140
−160
0
10
20
f − Frequency − MHz
Figure 8.
30
G057
−160
0
10
20
f − Frequency − MHz
Figure 9.
30
G058
100
96
92
88
84
80
76
72
68
64
60
0
SFDR vs INPUT FREQUENCY
Gain = 3.5 dB
Gain = 0 dB
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G059
Figure 10.
SNR vs INPUT FREQUENCY
76
74
72
Gain = 0 dB
70
Gain = 3.5 dB
68
66
64
62
0
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G060
Figure 11.
SFDR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
Gain = 3.5 dB
84
80
76
Gain = 0 dB
72
68
64
60
0 50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G061
Figure 12.
SNR vs INPUT FREQUENCY (LVDS interface)
76
74
Gain = 0 dB
72
70
Gain = 3.5 dB
68
66
64
62
0
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G062
Figure 13.
24
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