TM4C123GE6PM Datasheet, PDF (899/1408 Pages) Texas Instruments – Tiva™ TM4C123GE6PM Microcontroller

Tiva^™ TM4C123GE6PM Microcontroller
14.3.7
14.3.8
14.3.9
9-Bit UART Mode
The UART provides a 9-bit mode that is enabled with the 9BITEN bit in the UART9BITADDR
register. This feature is useful in a multi-drop configuration of the UART where a single master
connected to multiple slaves can communicate with a particular slave through its address or set of
addresses along with a qualifier for an address byte. All the slaves check for the address qualifier
in the place of the parity bit and, if set, then compare the byte received with the preprogrammed
address. If the address matches, then it receives or sends further data. If the address does not
match, it drops the address byte and any subsequent data bytes. If the UART is in 9-bit mode, then
the receiver operates with no parity mode. The address can be predefined to match with the received
byte and it can be configured with the UART9BITADDR register. The matching can be extended
to a set of addresses using the address mask in the UART9BITAMASK register. By default, the
UART9BITAMASK is 0xFF, meaning that only the specified address is matched.
When not finding a match, the rest of the data bytes with the 9th bit cleared are dropped. If a match
is found, then an interrupt is generated to the NVIC for further action. The subsequent data bytes
with the cleared 9th bit are stored in the FIFO. Software can mask this interrupt in case μDMA and/or
FIFO operations are enabled for this instance and processor intervention is not required. All the
send transactions with 9-bit mode are data bytes and the 9th bit is cleared. Software can override
the 9th bit to be set (to indicate address) by overriding the parity settings to sticky parity with odd
parity enabled for a particular byte. To match the transmission time with correct parity settings, the
address byte can be transmitted as a single then a burst transfer. The Transmit FIFO does not hold
the address/data bit, hence software should take care of enabling the address bit appropriately.
FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 905). Read operations of the UARTDR register return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 915).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 910) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 921). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example,
if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
June 12, 2014
899
Texas Instruments-Production Data