TM4C1237D5PZ Datasheet, PDF (891/1306 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237D5PZ Microcontroller
14.3.8
14.3.9
address byte can be transmitted as a single then a burst transfer. The Transmit FIFO does not hold
the address/data bit, hence software should take care of enabling the address bit appropriately.
FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 897). Read operations of the UARTDR register return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 908).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 902) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 914). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example,
if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 922).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 916) by setting the corresponding IM bits. If interrupts are not
used, the raw interrupt status is visible via the UART Raw Interrupt Status (UARTRIS) register
(see page 919).
Note: For receive timeout, the RTIM bit in the UARTIM register must be set to see the RTMIS and
RTRIS status in the UARTMIS and UARTRIS registers.
June 12, 2014
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