TMS320VC5421_17 Datasheet, PDF (88/104 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)^†
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV) Hold time, BDR valid after BCLKX high
12
2 − 12H
ns
4
6 +12H
ns
tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high
10
ns
tc(BCKX)
Cycle time, BCLKX
12H
32H
ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)^†
PARAMETER
MASTER^‡
MIN MAX
SLAVE
UNIT
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high¶
C−5 C+6
ns
T−5 T+5
ns
td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid
−3
12 6H + 4 10H + 19 ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from BCLKX
low
−6
10 6H + 4 10H + 17 ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D − 2 D +10 4H + 4 8H + 17 ns
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{T = BCLKX period = (1 + CLKGDV) * 2H}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
BFSX
BDX
BDR
LSB
tsu(BFXL-BCKXH)
MSB
tc(BCKX)
th(BCKXL-BFXL)
td(BFXL-BCKXH)
Bit 0
Bit 0
tdis(BCKXL-BDXHZ)
td(BFXL-BDXV)
tsu(BDRV-BCKXH)
Bit(n-1)
Bit(n-1)
td(BCKXL-BDXV)
(n-2)
(n-3)
th(BCKXH-BDRV)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
88 SPRS098D
December 1999 − Revised October 2008