DAC3482_15 Datasheet, PDF (88/106 Pages) Texas Instruments – DAC3482, Dual-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3482
SLAS748F – MARCH 2011 – REVISED AUGUST 2015
www.ti.com
9 Power Supply Recommendations
As shown in Figure 99, the DAC3482 device has various power rails and has two primary voltages of 1.2 V and
3.3 V. Some of the DAC power rails such as CLKVDD and AVDD are more noise sensitive than other rails
because they are mainly powering the switch drivers for the current switch array and the current bias circuits,
respectively. These circuits are the main analog DAC core. Any power supply noises such as switching power
supply ripple may be modulated directly onto the signal of interest. These two power rails should be powered by
low noise power supplies such as LDO. Powering the rail directly with switching power supplies is not
recommended for these two rails.
Sample Clock
Powered by CLKVDD
IOUTP
IOUTN
DAC
=
Switch
Array
Powered by DACVDD
Powered by
AVDD
Bias
Circuit
Current
Source Array
Figure 99. Interpolation Filters, NCOs, and QMC Blocks Powered by DIGVDD
With the DAC3482 being a mixed signal device, the device contains circuits that bridges the digital section and
the analog section. The DACVDD powers these sections. System designer can design this rail in secondary
priority. Powering the rail with LDO is recommended. Unless system designer pays special care to supply filtering
and power supply routing/placement, powering the rail directly with switching power supplies is not
recommended for this rail.
Since digital circuits have more inherent noise immunity than analog circuits, the power supply noise
requirements for DIGVDD of the digital section of the device may be relaxed and placed at a lower priority.
Depending on the spur level requirement, routing and placement of the power supply, power the rail directly with
switching power supplies can be possible. With the digital logics running, the DIGVDD rail may draw significant
current. If the power supply traces and filtering network have significant DC resistance loss (for example, DCR),
then the final supply voltage seen by the DIGVDD rail may not be sufficient to meet the minimum power supply
level. For instance, with 450 mA of DIGVDD current and about 0.1 Ω of DCR from the ferrite bead, the final
supply voltage at the DIGVDD pins may be 1.2 V – 0.045 V = 1.155 V. This is fairly close to the minimum supply
voltage range of 1.14 V. System designer may need to elevate the power supply voltage according to the DCR
level or design a feedback network for the power supply to account for associated voltage drop. To ensure power
supply accuracy and to account for power supply filter network loss at operating conditions, the use of the
ATEST function in register config27 to check the internal power supply nodes is recommended.
The table below is a summary of the various power supply nodes of the DAC. Care should be taken to keep
clean power supplies routing away from noisy digital supplies. It is recommended to use at least two power
layers. Power supplies for digital circuits tend to have more switching activities and are typically noisier, and
system designer should avoid sharing the digital power rail (for example, power supplies for FPGA or DIGVDD of
DAC3482) with the analog power rail (for example, CLKVDD and AVDD of DAC3482). Avoid placing noisy
supplies and clean supplies on adjacent board layers and use a ground layer between these two supplies if
possible. All supply pins should be decoupled as close to the pins as possible by using small value capacitors,
with larger bulk capacitors placed further away and near the power supply source.
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